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Macros</h2></td></tr>
<tr class="memitem:gafd5cde340aa4524c2bab0f5c570bf542"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gafd5cde340aa4524c2bab0f5c570bf542">XDSI_MAX_LANES</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:gafd5cde340aa4524c2bab0f5c570bf542"><td class="mdescLeft">&#160;</td><td class="mdescRight">Max Lanes supported by DSI.  <a href="group__dsi.html#gafd5cde340aa4524c2bab0f5c570bf542">More...</a><br/></td></tr>
<tr class="separator:gafd5cde340aa4524c2bab0f5c570bf542"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register sets of MIPI DSI Tx </p>
</div></td></tr>
<tr class="memitem:gaeed29761e55d0d1bbe7760684481a396"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaeed29761e55d0d1bbe7760684481a396">XDSI_CCR_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:gaeed29761e55d0d1bbe7760684481a396"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Configuration Register Offset.  <a href="group__dsi.html#gaeed29761e55d0d1bbe7760684481a396">More...</a><br/></td></tr>
<tr class="separator:gaeed29761e55d0d1bbe7760684481a396"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5473a7e6d9e1d01a628e9626c9ade095"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga5473a7e6d9e1d01a628e9626c9ade095">XDSI_PCR_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga5473a7e6d9e1d01a628e9626c9ade095"><td class="mdescLeft">&#160;</td><td class="mdescRight">Protocol Configuration Register Offset.  <a href="group__dsi.html#ga5473a7e6d9e1d01a628e9626c9ade095">More...</a><br/></td></tr>
<tr class="separator:ga5473a7e6d9e1d01a628e9626c9ade095"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadfe1bdf3d5aa5eec603cbafa671558f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gadfe1bdf3d5aa5eec603cbafa671558f9">XDSI_GIER_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gadfe1bdf3d5aa5eec603cbafa671558f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Register Offset.  <a href="group__dsi.html#gadfe1bdf3d5aa5eec603cbafa671558f9">More...</a><br/></td></tr>
<tr class="separator:gadfe1bdf3d5aa5eec603cbafa671558f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb8fcfb941281bff18fdf99901624f50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gacb8fcfb941281bff18fdf99901624f50">XDSI_ISR_OFFSET</a>&#160;&#160;&#160;0x00000024</td></tr>
<tr class="memdesc:gacb8fcfb941281bff18fdf99901624f50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register.  <a href="group__dsi.html#gacb8fcfb941281bff18fdf99901624f50">More...</a><br/></td></tr>
<tr class="separator:gacb8fcfb941281bff18fdf99901624f50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c9dabd1df1c9bbbe2f07d6886b0d08e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga7c9dabd1df1c9bbbe2f07d6886b0d08e">XDSI_IER_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:ga7c9dabd1df1c9bbbe2f07d6886b0d08e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Register.  <a href="group__dsi.html#ga7c9dabd1df1c9bbbe2f07d6886b0d08e">More...</a><br/></td></tr>
<tr class="separator:ga7c9dabd1df1c9bbbe2f07d6886b0d08e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3eec9707c024afb9195332aebdf1af60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga3eec9707c024afb9195332aebdf1af60">XDSI_STATUS_OFFSET</a>&#160;&#160;&#160;0x0000002C</td></tr>
<tr class="memdesc:ga3eec9707c024afb9195332aebdf1af60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register.  <a href="group__dsi.html#ga3eec9707c024afb9195332aebdf1af60">More...</a><br/></td></tr>
<tr class="separator:ga3eec9707c024afb9195332aebdf1af60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga756164904eef9cd3ebee25d94e973236"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga756164904eef9cd3ebee25d94e973236">XDSI_COMMAND_OFFSET</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:ga756164904eef9cd3ebee25d94e973236"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Entry to command Queue.  <a href="group__dsi.html#ga756164904eef9cd3ebee25d94e973236">More...</a><br/></td></tr>
<tr class="separator:ga756164904eef9cd3ebee25d94e973236"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bca0e71c69c9b8dd7b02928754671e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga8bca0e71c69c9b8dd7b02928754671e1">XDSI_DATA_OFFSET</a>&#160;&#160;&#160;0x00000034</td></tr>
<tr class="memdesc:ga8bca0e71c69c9b8dd7b02928754671e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Data to data Queue.  <a href="group__dsi.html#ga8bca0e71c69c9b8dd7b02928754671e1">More...</a><br/></td></tr>
<tr class="separator:ga8bca0e71c69c9b8dd7b02928754671e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4a366cd8b489f2300cf007185d74c6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gac4a366cd8b489f2300cf007185d74c6a">XDSI_TIME1_OFFSET</a>&#160;&#160;&#160;0x00000050</td></tr>
<tr class="memdesc:gac4a366cd8b489f2300cf007185d74c6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time 1 Offset.  <a href="group__dsi.html#gac4a366cd8b489f2300cf007185d74c6a">More...</a><br/></td></tr>
<tr class="separator:gac4a366cd8b489f2300cf007185d74c6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae376be8a524a2ed0c89edbbd4ef69e12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gae376be8a524a2ed0c89edbbd4ef69e12">XDSI_TIME2_OFFSET</a>&#160;&#160;&#160;0x00000054</td></tr>
<tr class="memdesc:gae376be8a524a2ed0c89edbbd4ef69e12"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time 2 Offset.  <a href="group__dsi.html#gae376be8a524a2ed0c89edbbd4ef69e12">More...</a><br/></td></tr>
<tr class="separator:gae376be8a524a2ed0c89edbbd4ef69e12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac71b3e52fa7de0307f51ab1f7131f732"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gac71b3e52fa7de0307f51ab1f7131f732">XDSI_TIME3_OFFSET</a>&#160;&#160;&#160;0x00000058</td></tr>
<tr class="memdesc:gac71b3e52fa7de0307f51ab1f7131f732"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time 3 Offset.  <a href="group__dsi.html#gac71b3e52fa7de0307f51ab1f7131f732">More...</a><br/></td></tr>
<tr class="separator:gac71b3e52fa7de0307f51ab1f7131f732"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85afc2d5f71f5a75f74c2011189e3dce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga85afc2d5f71f5a75f74c2011189e3dce">XDSI_TIME4_OFFSET</a>&#160;&#160;&#160;0x0000005C</td></tr>
<tr class="memdesc:ga85afc2d5f71f5a75f74c2011189e3dce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time 4 Offset.  <a href="group__dsi.html#ga85afc2d5f71f5a75f74c2011189e3dce">More...</a><br/></td></tr>
<tr class="separator:ga85afc2d5f71f5a75f74c2011189e3dce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga59b5452a5b5f1076b77a024729ef910d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga59b5452a5b5f1076b77a024729ef910d">XDSI_LTIME_OFFSET</a>&#160;&#160;&#160;0x00000060</td></tr>
<tr class="memdesc:ga59b5452a5b5f1076b77a024729ef910d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Total Line Timing Offset.  <a href="group__dsi.html#ga59b5452a5b5f1076b77a024729ef910d">More...</a><br/></td></tr>
<tr class="separator:ga59b5452a5b5f1076b77a024729ef910d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac838501f9d54d130a9b3599b7b9117f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gac838501f9d54d130a9b3599b7b9117f8">XDSI_BLLP_TIME_OFFSET</a>&#160;&#160;&#160;0x00000064</td></tr>
<tr class="memdesc:gac838501f9d54d130a9b3599b7b9117f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">BLLP Time duration Offset.  <a href="group__dsi.html#gac838501f9d54d130a9b3599b7b9117f8">More...</a><br/></td></tr>
<tr class="separator:gac838501f9d54d130a9b3599b7b9117f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2a81ddc1c99113e94de75b17bb9a7b83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga2a81ddc1c99113e94de75b17bb9a7b83">XDSI_TIME5_OFFSET</a>&#160;&#160;&#160;0x0000006C</td></tr>
<tr class="memdesc:ga2a81ddc1c99113e94de75b17bb9a7b83"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time 5 Offset.  <a href="group__dsi.html#ga2a81ddc1c99113e94de75b17bb9a7b83">More...</a><br/></td></tr>
<tr class="separator:ga2a81ddc1c99113e94de75b17bb9a7b83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Core configuration register masks and shifts</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used for the enabling/disabling and resetting the core of DSI Tx Controller </p>
</div></td></tr>
<tr class="memitem:gaadb37754348b511601dea7506119f57b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaadb37754348b511601dea7506119f57b">XDSI_CCR_RESET_CMD_FIFO_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gaadb37754348b511601dea7506119f57b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command FIFO Reset bit Mask.  <a href="group__dsi.html#gaadb37754348b511601dea7506119f57b">More...</a><br/></td></tr>
<tr class="separator:gaadb37754348b511601dea7506119f57b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac66acd11ef45354f249a3a08779e5da5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gac66acd11ef45354f249a3a08779e5da5">XDSI_CCR_RESET_DATA_FIFO_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gac66acd11ef45354f249a3a08779e5da5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data FIFO Reset bit Mask.  <a href="group__dsi.html#gac66acd11ef45354f249a3a08779e5da5">More...</a><br/></td></tr>
<tr class="separator:gac66acd11ef45354f249a3a08779e5da5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d0c1ae0c0d9924987be74d0c7000265"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga1d0c1ae0c0d9924987be74d0c7000265">XDSI_CCR_CRREADY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga1d0c1ae0c0d9924987be74d0c7000265"><td class="mdescLeft">&#160;</td><td class="mdescRight">Controller Ready bit Mask.  <a href="group__dsi.html#ga1d0c1ae0c0d9924987be74d0c7000265">More...</a><br/></td></tr>
<tr class="separator:ga1d0c1ae0c0d9924987be74d0c7000265"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa2a45eef681d96a7a2d4e36531589db8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaa2a45eef681d96a7a2d4e36531589db8">XDSI_CCR_SOFTRESET_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaa2a45eef681d96a7a2d4e36531589db8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Soft Reset core bit Mask.  <a href="group__dsi.html#gaa2a45eef681d96a7a2d4e36531589db8">More...</a><br/></td></tr>
<tr class="separator:gaa2a45eef681d96a7a2d4e36531589db8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27e3fe15791633934c2362977de80c5d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga27e3fe15791633934c2362977de80c5d">XDSI_CCR_COREENB_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga27e3fe15791633934c2362977de80c5d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable core Mask.  <a href="group__dsi.html#ga27e3fe15791633934c2362977de80c5d">More...</a><br/></td></tr>
<tr class="separator:ga27e3fe15791633934c2362977de80c5d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga293abcb77d98384a12dd86ea038bd50c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga293abcb77d98384a12dd86ea038bd50c">XDSI_CCR_CORECMDMODE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga293abcb77d98384a12dd86ea038bd50c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable Command/video mode Mask.  <a href="group__dsi.html#ga293abcb77d98384a12dd86ea038bd50c">More...</a><br/></td></tr>
<tr class="separator:ga293abcb77d98384a12dd86ea038bd50c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2901893d8342311d6ddb9f507ef7ae2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaf2901893d8342311d6ddb9f507ef7ae2">XDSI_CCR_CORECMDMODE_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gaf2901893d8342311d6ddb9f507ef7ae2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for selection of command/video mode.  <a href="group__dsi.html#gaf2901893d8342311d6ddb9f507ef7ae2">More...</a><br/></td></tr>
<tr class="separator:gaf2901893d8342311d6ddb9f507ef7ae2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0933ad53dc42710435be79ad4316720d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga0933ad53dc42710435be79ad4316720d">XDSI_CCR_CRREADY_SHIFT</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga0933ad53dc42710435be79ad4316720d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Controller Ready.  <a href="group__dsi.html#ga0933ad53dc42710435be79ad4316720d">More...</a><br/></td></tr>
<tr class="separator:ga0933ad53dc42710435be79ad4316720d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1f2d881102a20feb2fa29e29018eaa53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga1f2d881102a20feb2fa29e29018eaa53">XDSI_CCR_SOFTRESET_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga1f2d881102a20feb2fa29e29018eaa53"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Soft reset.  <a href="group__dsi.html#ga1f2d881102a20feb2fa29e29018eaa53">More...</a><br/></td></tr>
<tr class="separator:ga1f2d881102a20feb2fa29e29018eaa53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabebe3e1ad24a94fe95a71eaecb51d037"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gabebe3e1ad24a94fe95a71eaecb51d037">XDSI_CCR_COREENB_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gabebe3e1ad24a94fe95a71eaecb51d037"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Core Enable.  <a href="group__dsi.html#gabebe3e1ad24a94fe95a71eaecb51d037">More...</a><br/></td></tr>
<tr class="separator:gabebe3e1ad24a94fe95a71eaecb51d037"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and shifts of Protocol control register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register reports the number of lanes configured during core generation and number of lanes actively used. </p>
</div></td></tr>
<tr class="memitem:gabc0ff6dc79f1ebd472b213955331d771"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gabc0ff6dc79f1ebd472b213955331d771">XDSI_PCR_EOTPENABLE_MASK</a>&#160;&#160;&#160;0x00002000</td></tr>
<tr class="memdesc:gabc0ff6dc79f1ebd472b213955331d771"><td class="mdescLeft">&#160;</td><td class="mdescRight">End of Transmission Mask bit.  <a href="group__dsi.html#gabc0ff6dc79f1ebd472b213955331d771">More...</a><br/></td></tr>
<tr class="separator:gabc0ff6dc79f1ebd472b213955331d771"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9578dc1efc2845eb63a46bd5b0927a9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga9578dc1efc2845eb63a46bd5b0927a9a">XDSI_PCR_PIXELFORMAT_MASK</a>&#160;&#160;&#160;0x00001F80</td></tr>
<tr class="memdesc:ga9578dc1efc2845eb63a46bd5b0927a9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pixel Format Type Bit Mask.  <a href="group__dsi.html#ga9578dc1efc2845eb63a46bd5b0927a9a">More...</a><br/></td></tr>
<tr class="separator:ga9578dc1efc2845eb63a46bd5b0927a9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8ae113e8b2d35582f48aae14848a9ec2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga8ae113e8b2d35582f48aae14848a9ec2">XDSI_PCR_BLLPMODE_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga8ae113e8b2d35582f48aae14848a9ec2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Blank packet Mode Bit Mask.  <a href="group__dsi.html#ga8ae113e8b2d35582f48aae14848a9ec2">More...</a><br/></td></tr>
<tr class="separator:ga8ae113e8b2d35582f48aae14848a9ec2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6ef282e9923450aa24813440b0d3166d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga6ef282e9923450aa24813440b0d3166d">XDSI_PCR_BLLPTYPE_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga6ef282e9923450aa24813440b0d3166d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Blank packet type Bit Mask.  <a href="group__dsi.html#ga6ef282e9923450aa24813440b0d3166d">More...</a><br/></td></tr>
<tr class="separator:ga6ef282e9923450aa24813440b0d3166d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga271f39b4ede2adc787ac512d872a1466"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga271f39b4ede2adc787ac512d872a1466">XDSI_PCR_VIDEOMODE_MASK</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:ga271f39b4ede2adc787ac512d872a1466"><td class="mdescLeft">&#160;</td><td class="mdescRight">Video mode Type Bit Mask.  <a href="group__dsi.html#ga271f39b4ede2adc787ac512d872a1466">More...</a><br/></td></tr>
<tr class="separator:ga271f39b4ede2adc787ac512d872a1466"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad55a48efbc25b1d31fdd14c855cd4531"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gad55a48efbc25b1d31fdd14c855cd4531">XDSI_PCR_ACTLANES_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gad55a48efbc25b1d31fdd14c855cd4531"><td class="mdescLeft">&#160;</td><td class="mdescRight">Active lanes in core.  <a href="group__dsi.html#gad55a48efbc25b1d31fdd14c855cd4531">More...</a><br/></td></tr>
<tr class="separator:gad55a48efbc25b1d31fdd14c855cd4531"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c2438103e15a67ad1a3d871da9df8c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga8c2438103e15a67ad1a3d871da9df8c3">XDSI_PCR_EOTPENABLE_SHIFT</a>&#160;&#160;&#160;13</td></tr>
<tr class="memdesc:ga8c2438103e15a67ad1a3d871da9df8c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for EOTP Enable.  <a href="group__dsi.html#ga8c2438103e15a67ad1a3d871da9df8c3">More...</a><br/></td></tr>
<tr class="separator:ga8c2438103e15a67ad1a3d871da9df8c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf99ead6a914f18003e6d17d21ef1339"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gacf99ead6a914f18003e6d17d21ef1339">XDSI_PCR_PIXELFORMAT_SHIFT</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:gacf99ead6a914f18003e6d17d21ef1339"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for pixel format.  <a href="group__dsi.html#gacf99ead6a914f18003e6d17d21ef1339">More...</a><br/></td></tr>
<tr class="separator:gacf99ead6a914f18003e6d17d21ef1339"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga601afb13b1b8b27b9b6d7ba8ab7972d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga601afb13b1b8b27b9b6d7ba8ab7972d7">XDSI_PCR_BLLPMODE_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga601afb13b1b8b27b9b6d7ba8ab7972d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Blank packet Type.  <a href="group__dsi.html#ga601afb13b1b8b27b9b6d7ba8ab7972d7">More...</a><br/></td></tr>
<tr class="separator:ga601afb13b1b8b27b9b6d7ba8ab7972d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72fda4b1dfd3be762e1f9edb46cd4cbb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga72fda4b1dfd3be762e1f9edb46cd4cbb">XDSI_PCR_BLLPTYPE_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:ga72fda4b1dfd3be762e1f9edb46cd4cbb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Blank packet Type.  <a href="group__dsi.html#ga72fda4b1dfd3be762e1f9edb46cd4cbb">More...</a><br/></td></tr>
<tr class="separator:ga72fda4b1dfd3be762e1f9edb46cd4cbb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad869da63d8dcc972866d7ab606f62a73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gad869da63d8dcc972866d7ab606f62a73">XDSI_PCR_VIDEOMODE_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gad869da63d8dcc972866d7ab606f62a73"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Max Lanes.  <a href="group__dsi.html#gad869da63d8dcc972866d7ab606f62a73">More...</a><br/></td></tr>
<tr class="separator:gad869da63d8dcc972866d7ab606f62a73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0417ad9ef1605a2752057a21b96ebc6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga0417ad9ef1605a2752057a21b96ebc6a">XDSI_PCR_ACTLANES_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga0417ad9ef1605a2752057a21b96ebc6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Active Lanes.  <a href="group__dsi.html#ga0417ad9ef1605a2752057a21b96ebc6a">More...</a><br/></td></tr>
<tr class="separator:ga0417ad9ef1605a2752057a21b96ebc6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and shift of XDSI_STSTUS_OFFSET</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register used to get Command Queue Vacancy </p>
</div></td></tr>
<tr class="memitem:ga36f238f2ceee886fc755d2a057189b35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga36f238f2ceee886fc755d2a057189b35">XDSI_UNDER_PROCESS_MASK</a>&#160;&#160;&#160;0x00001000</td></tr>
<tr class="memdesc:ga36f238f2ceee886fc755d2a057189b35"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Underprocess.  <a href="group__dsi.html#ga36f238f2ceee886fc755d2a057189b35">More...</a><br/></td></tr>
<tr class="separator:ga36f238f2ceee886fc755d2a057189b35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac8dfac9fbbdfce6886d2d4189c391df6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gac8dfac9fbbdfce6886d2d4189c391df6">XDSI_INPOGRESS_MASK</a>&#160;&#160;&#160;0x00000800</td></tr>
<tr class="memdesc:gac8dfac9fbbdfce6886d2d4189c391df6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command InProgress.  <a href="group__dsi.html#gac8dfac9fbbdfce6886d2d4189c391df6">More...</a><br/></td></tr>
<tr class="separator:gac8dfac9fbbdfce6886d2d4189c391df6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabbcdc991f6f72d20762ac965ba467049"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gabbcdc991f6f72d20762ac965ba467049">XDSI_WAIT_FOR_DATA_MASK</a>&#160;&#160;&#160;0x00000400</td></tr>
<tr class="memdesc:gabbcdc991f6f72d20762ac965ba467049"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait for Long packet data.  <a href="group__dsi.html#gabbcdc991f6f72d20762ac965ba467049">More...</a><br/></td></tr>
<tr class="separator:gabbcdc991f6f72d20762ac965ba467049"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga036623217c7b18b8d4dcc50bde420a9d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga036623217c7b18b8d4dcc50bde420a9d">XDSI_FIFO_EMPTY_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga036623217c7b18b8d4dcc50bde420a9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO EMPTY.  <a href="group__dsi.html#ga036623217c7b18b8d4dcc50bde420a9d">More...</a><br/></td></tr>
<tr class="separator:ga036623217c7b18b8d4dcc50bde420a9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d85a515b966aacb845649b21734104c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga7d85a515b966aacb845649b21734104c">XDSI_FIFO_FULL_MASK</a>&#160;&#160;&#160;0x00000100</td></tr>
<tr class="memdesc:ga7d85a515b966aacb845649b21734104c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO FULL.  <a href="group__dsi.html#ga7d85a515b966aacb845649b21734104c">More...</a><br/></td></tr>
<tr class="separator:ga7d85a515b966aacb845649b21734104c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga255f0b156b8387b6e74297c982cd05f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga255f0b156b8387b6e74297c982cd05f2">XDSI_RDY_FOR_LONG_MASK</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga255f0b156b8387b6e74297c982cd05f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Readiness for Long packet.  <a href="group__dsi.html#ga255f0b156b8387b6e74297c982cd05f2">More...</a><br/></td></tr>
<tr class="separator:ga255f0b156b8387b6e74297c982cd05f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0631ea66385f5d0aa0c5f0dba730edb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga0631ea66385f5d0aa0c5f0dba730edb9">XDSI_RDY_FOR_SHORT_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga0631ea66385f5d0aa0c5f0dba730edb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Readiness for short packet.  <a href="group__dsi.html#ga0631ea66385f5d0aa0c5f0dba730edb9">More...</a><br/></td></tr>
<tr class="separator:ga0631ea66385f5d0aa0c5f0dba730edb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2ef1d4a5206a3857ffa7f6f548395a44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga2ef1d4a5206a3857ffa7f6f548395a44">XDSI_CMDQ_MASK</a>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="memdesc:ga2ef1d4a5206a3857ffa7f6f548395a44"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Queue Vacancy.  <a href="group__dsi.html#ga2ef1d4a5206a3857ffa7f6f548395a44">More...</a><br/></td></tr>
<tr class="separator:ga2ef1d4a5206a3857ffa7f6f548395a44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa08ce23a53c58919c01b8dd7a9d946ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaa08ce23a53c58919c01b8dd7a9d946ca">XDSI_UNDER_PROCESS_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:gaa08ce23a53c58919c01b8dd7a9d946ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Underprocess.  <a href="group__dsi.html#gaa08ce23a53c58919c01b8dd7a9d946ca">More...</a><br/></td></tr>
<tr class="separator:gaa08ce23a53c58919c01b8dd7a9d946ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f362267832e7294ec490c1960f62a1e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga8f362267832e7294ec490c1960f62a1e">XDSI_INPOGRESS_SHIFT</a>&#160;&#160;&#160;11</td></tr>
<tr class="memdesc:ga8f362267832e7294ec490c1960f62a1e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command InProgress.  <a href="group__dsi.html#ga8f362267832e7294ec490c1960f62a1e">More...</a><br/></td></tr>
<tr class="separator:ga8f362267832e7294ec490c1960f62a1e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8d28adcc53611d9112c541daf7c99dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gab8d28adcc53611d9112c541daf7c99dc">XDSI_WAIT_FOR_DATA_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:gab8d28adcc53611d9112c541daf7c99dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wait for Long packet data.  <a href="group__dsi.html#gab8d28adcc53611d9112c541daf7c99dc">More...</a><br/></td></tr>
<tr class="separator:gab8d28adcc53611d9112c541daf7c99dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac94bb2023befdf9f08d9c67906b25ed8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gac94bb2023befdf9f08d9c67906b25ed8">XDSI_FIFO_EMPTY_SHIFT</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:gac94bb2023befdf9f08d9c67906b25ed8"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO EMPTY.  <a href="group__dsi.html#gac94bb2023befdf9f08d9c67906b25ed8">More...</a><br/></td></tr>
<tr class="separator:gac94bb2023befdf9f08d9c67906b25ed8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3e748a5f6166f59a28038e6e4d08a4e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga3e748a5f6166f59a28038e6e4d08a4e1">XDSI_FIFO_FULL_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga3e748a5f6166f59a28038e6e4d08a4e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO FULL.  <a href="group__dsi.html#ga3e748a5f6166f59a28038e6e4d08a4e1">More...</a><br/></td></tr>
<tr class="separator:ga3e748a5f6166f59a28038e6e4d08a4e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga92c7835aba118ea5684b4d9173da53ad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga92c7835aba118ea5684b4d9173da53ad">XDSI_RDY_FOR_LONGPKT_SHIFT</a>&#160;&#160;&#160;7</td></tr>
<tr class="memdesc:ga92c7835aba118ea5684b4d9173da53ad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Readiness for Long packet.  <a href="group__dsi.html#ga92c7835aba118ea5684b4d9173da53ad">More...</a><br/></td></tr>
<tr class="separator:ga92c7835aba118ea5684b4d9173da53ad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga309c3b6865650aee680f7c2f1c580e17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga309c3b6865650aee680f7c2f1c580e17">XDSI_RDY_FOR_SHORTPKT_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga309c3b6865650aee680f7c2f1c580e17"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command Queue Vacancy.  <a href="group__dsi.html#ga309c3b6865650aee680f7c2f1c580e17">More...</a><br/></td></tr>
<tr class="separator:ga309c3b6865650aee680f7c2f1c580e17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60dcf8b29cd972006ff5d5540fce8afc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga60dcf8b29cd972006ff5d5540fce8afc">XDSI_CMDQ_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga60dcf8b29cd972006ff5d5540fce8afc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Command Queue.  <a href="group__dsi.html#ga60dcf8b29cd972006ff5d5540fce8afc">More...</a><br/></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Bitmasks and shift of XDSI_TIME1_OFFSET</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register used to set timing parameters HSA and BLLP </p>
</div></td></tr>
<tr class="memitem:ga6ca60a035f038d32cc493b2add7658df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga6ca60a035f038d32cc493b2add7658df">XDSI_TIME1_HSA_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga6ca60a035f038d32cc493b2add7658df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Horizontal timing parameter HSA mask.  <a href="group__dsi.html#ga6ca60a035f038d32cc493b2add7658df">More...</a><br/></td></tr>
<tr class="separator:ga6ca60a035f038d32cc493b2add7658df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5121bc553dddc02a46d1217ae1f59cb2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga5121bc553dddc02a46d1217ae1f59cb2">XDSI_TIME1_BLLP_BURST_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga5121bc553dddc02a46d1217ae1f59cb2"><td class="mdescLeft">&#160;</td><td class="mdescRight">BLLP Packet size Mask bit.  <a href="group__dsi.html#ga5121bc553dddc02a46d1217ae1f59cb2">More...</a><br/></td></tr>
<tr class="separator:ga5121bc553dddc02a46d1217ae1f59cb2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fb7c2dbe962b133f786d99190bc9f64"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga7fb7c2dbe962b133f786d99190bc9f64">XDSI_TIME1_HSA_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga7fb7c2dbe962b133f786d99190bc9f64"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for HSA.  <a href="group__dsi.html#ga7fb7c2dbe962b133f786d99190bc9f64">More...</a><br/></td></tr>
<tr class="separator:ga7fb7c2dbe962b133f786d99190bc9f64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf929a8f5bc9aa8fb235dbee913b385c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaf929a8f5bc9aa8fb235dbee913b385c3">XDSI_TIME1_BLLP_BURST_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gaf929a8f5bc9aa8fb235dbee913b385c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for BLLP.  <a href="group__dsi.html#gaf929a8f5bc9aa8fb235dbee913b385c3">More...</a><br/></td></tr>
<tr class="separator:gaf929a8f5bc9aa8fb235dbee913b385c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and shift of XDSI_TIME2_OFFSET</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register used to set timing parameters </p>
</div></td></tr>
<tr class="memitem:gabcd683e6c5c0ddca8d83b961c1c27571"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gabcd683e6c5c0ddca8d83b961c1c27571">XDSI_TIME2_HACT_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:gabcd683e6c5c0ddca8d83b961c1c27571"><td class="mdescLeft">&#160;</td><td class="mdescRight">Horizontal timing parameter HACT Bit Mask.  <a href="group__dsi.html#gabcd683e6c5c0ddca8d83b961c1c27571">More...</a><br/></td></tr>
<tr class="separator:gabcd683e6c5c0ddca8d83b961c1c27571"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga23fd9aec9678b9edee648c802e432708"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga23fd9aec9678b9edee648c802e432708">XDSI_TIME2_VACT_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga23fd9aec9678b9edee648c802e432708"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vertical timing parameter VACT.  <a href="group__dsi.html#ga23fd9aec9678b9edee648c802e432708">More...</a><br/></td></tr>
<tr class="separator:ga23fd9aec9678b9edee648c802e432708"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaa4ff48185c352ee4048528679f61f0f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaaa4ff48185c352ee4048528679f61f0f">XDSI_TIME2_HACT_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gaaa4ff48185c352ee4048528679f61f0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for HACT.  <a href="group__dsi.html#gaaa4ff48185c352ee4048528679f61f0f">More...</a><br/></td></tr>
<tr class="separator:gaaa4ff48185c352ee4048528679f61f0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98f744957ce0523887308d0d240d62e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga98f744957ce0523887308d0d240d62e7">XDSI_TIME2_VACT_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga98f744957ce0523887308d0d240d62e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for VACT.  <a href="group__dsi.html#ga98f744957ce0523887308d0d240d62e7">More...</a><br/></td></tr>
<tr class="separator:ga98f744957ce0523887308d0d240d62e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and shift of XDSI_TIME3_OFFSET</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register used to set timing parameters </p>
</div></td></tr>
<tr class="memitem:ga78c45e2c8728415dfab29796abd2c7bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga78c45e2c8728415dfab29796abd2c7bc">XDSI_TIME3_HBP_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga78c45e2c8728415dfab29796abd2c7bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Horizontal timing parameter HBP Bit Mask.  <a href="group__dsi.html#ga78c45e2c8728415dfab29796abd2c7bc">More...</a><br/></td></tr>
<tr class="separator:ga78c45e2c8728415dfab29796abd2c7bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb2b93d556f6bb2e46c31147cea739be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaeb2b93d556f6bb2e46c31147cea739be">XDSI_TIME3_HFP_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:gaeb2b93d556f6bb2e46c31147cea739be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Horizontal timing parameter HFP.  <a href="group__dsi.html#gaeb2b93d556f6bb2e46c31147cea739be">More...</a><br/></td></tr>
<tr class="separator:gaeb2b93d556f6bb2e46c31147cea739be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0a805d66d6f6f2bf59097b029e6b431d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga0a805d66d6f6f2bf59097b029e6b431d">XDSI_TIME3_HBP_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga0a805d66d6f6f2bf59097b029e6b431d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for HBP.  <a href="group__dsi.html#ga0a805d66d6f6f2bf59097b029e6b431d">More...</a><br/></td></tr>
<tr class="separator:ga0a805d66d6f6f2bf59097b029e6b431d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga067a2b160256964ed106a368a8b076ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga067a2b160256964ed106a368a8b076ab">XDSI_TIME3_HFP_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga067a2b160256964ed106a368a8b076ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for HFP.  <a href="group__dsi.html#ga067a2b160256964ed106a368a8b076ab">More...</a><br/></td></tr>
<tr class="separator:ga067a2b160256964ed106a368a8b076ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offset of XDSI_TIME4_OFFSET</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register used to set Vertical timing parameters </p>
</div></td></tr>
<tr class="memitem:gabedf15b8f6fccd8079018080ae7a5c33"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gabedf15b8f6fccd8079018080ae7a5c33">XDSI_TIME4_VSA_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gabedf15b8f6fccd8079018080ae7a5c33"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time 4 Vertical Sync Active Mask.  <a href="group__dsi.html#gabedf15b8f6fccd8079018080ae7a5c33">More...</a><br/></td></tr>
<tr class="separator:gabedf15b8f6fccd8079018080ae7a5c33"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4997aca9165c650931dd9db4ff8a8030"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga4997aca9165c650931dd9db4ff8a8030">XDSI_TIME4_VBP_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:ga4997aca9165c650931dd9db4ff8a8030"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vertical timing parameter1 VBP.  <a href="group__dsi.html#ga4997aca9165c650931dd9db4ff8a8030">More...</a><br/></td></tr>
<tr class="separator:ga4997aca9165c650931dd9db4ff8a8030"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc660200910868714ec0c22d555237d0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gacc660200910868714ec0c22d555237d0">XDSI_TIME4_VFP_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:gacc660200910868714ec0c22d555237d0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vertical timing parameter1 VFP.  <a href="group__dsi.html#gacc660200910868714ec0c22d555237d0">More...</a><br/></td></tr>
<tr class="separator:gacc660200910868714ec0c22d555237d0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae176d9e5d32984f3954dc074a8b61c18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gae176d9e5d32984f3954dc074a8b61c18">XDSI_TIME4_VSA_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gae176d9e5d32984f3954dc074a8b61c18"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for VSA.  <a href="group__dsi.html#gae176d9e5d32984f3954dc074a8b61c18">More...</a><br/></td></tr>
<tr class="separator:gae176d9e5d32984f3954dc074a8b61c18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa40458dc22549ca1926f00e1e4621dcc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaa40458dc22549ca1926f00e1e4621dcc">XDSI_TIME4_VBP_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gaa40458dc22549ca1926f00e1e4621dcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for VBP.  <a href="group__dsi.html#gaa40458dc22549ca1926f00e1e4621dcc">More...</a><br/></td></tr>
<tr class="separator:gaa40458dc22549ca1926f00e1e4621dcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga675c207e160bff65bb13acfb61a880fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga675c207e160bff65bb13acfb61a880fe">XDSI_TIME4_VFP_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga675c207e160bff65bb13acfb61a880fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for VFP.  <a href="group__dsi.html#ga675c207e160bff65bb13acfb61a880fe">More...</a><br/></td></tr>
<tr class="separator:ga675c207e160bff65bb13acfb61a880fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offset of XDSI_TIME5_OFFSET</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register used to set Extended vertical timing parameters It stores MSB 8-bits of 16-bit Vertical front porch lines count. </p>
</div></td></tr>
<tr class="memitem:gae9213567f832c907adcde9bc546db5b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gae9213567f832c907adcde9bc546db5b7">XDSI_TIME5_VFP_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:gae9213567f832c907adcde9bc546db5b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Vertical extended timing parameter1 VFP.  <a href="group__dsi.html#gae9213567f832c907adcde9bc546db5b7">More...</a><br/></td></tr>
<tr class="separator:gae9213567f832c907adcde9bc546db5b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaed4f0786b4332c55c442d182ba078c86"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaed4f0786b4332c55c442d182ba078c86">XDSI_TIME5_VFP_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gaed4f0786b4332c55c442d182ba078c86"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for VFP.  <a href="group__dsi.html#gaed4f0786b4332c55c442d182ba078c86">More...</a><br/></td></tr>
<tr class="separator:gaed4f0786b4332c55c442d182ba078c86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDSI_GIER_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the global interrupt enable bit. </p>
</div></td></tr>
<tr class="memitem:ga38a82b5413fb14f7872ce10d00219173"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga38a82b5413fb14f7872ce10d00219173">XDSI_GIER_GIE_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga38a82b5413fb14f7872ce10d00219173"><td class="mdescLeft">&#160;</td><td class="mdescRight">Global Interrupt Enable bit.  <a href="group__dsi.html#ga38a82b5413fb14f7872ce10d00219173">More...</a><br/></td></tr>
<tr class="separator:ga38a82b5413fb14f7872ce10d00219173"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6bef15fcaa516e04f937b6247da6995b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga6bef15fcaa516e04f937b6247da6995b">XDSI_GIER_GIE_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga6bef15fcaa516e04f937b6247da6995b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift bits for Global Interrupt Enable.  <a href="group__dsi.html#ga6bef15fcaa516e04f937b6247da6995b">More...</a><br/></td></tr>
<tr class="separator:ga6bef15fcaa516e04f937b6247da6995b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f97ebd699329e463492b51665c17552"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga3f97ebd699329e463492b51665c17552">XDSI_GIER_SET</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga3f97ebd699329e463492b51665c17552"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the Global Interrupts.  <a href="group__dsi.html#ga3f97ebd699329e463492b51665c17552">More...</a><br/></td></tr>
<tr class="separator:ga3f97ebd699329e463492b51665c17552"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5e9a10da2d0caec73176b123a921c0d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga5e9a10da2d0caec73176b123a921c0d6">XDSI_GIER_RESET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga5e9a10da2d0caec73176b123a921c0d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the Global Interrupts.  <a href="group__dsi.html#ga5e9a10da2d0caec73176b123a921c0d6">More...</a><br/></td></tr>
<tr class="separator:ga5e9a10da2d0caec73176b123a921c0d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDSI_ISR_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the interrupt status. </p>
</div></td></tr>
<tr class="memitem:ga864795811a1e6e6c3aa4e0dfed0c36c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga864795811a1e6e6c3aa4e0dfed0c36c1">XDSI_ISR_CMDQ_FIFO_FULL_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga864795811a1e6e6c3aa4e0dfed0c36c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command queue vacancy full.  <a href="group__dsi.html#ga864795811a1e6e6c3aa4e0dfed0c36c1">More...</a><br/></td></tr>
<tr class="separator:ga864795811a1e6e6c3aa4e0dfed0c36c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga04f7b4ea5744fd64820837635a0bf6a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga04f7b4ea5744fd64820837635a0bf6a8">XDSI_ISR_DATA_ID_ERR_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga04f7b4ea5744fd64820837635a0bf6a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unsupport datatype Error.  <a href="group__dsi.html#ga04f7b4ea5744fd64820837635a0bf6a8">More...</a><br/></td></tr>
<tr class="separator:ga04f7b4ea5744fd64820837635a0bf6a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa767ee25aa648007b1341d7fcaa492f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaa767ee25aa648007b1341d7fcaa492f7">XDSI_ISR_PXL_UNDR_RUN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaa767ee25aa648007b1341d7fcaa492f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pixel under run error.  <a href="group__dsi.html#gaa767ee25aa648007b1341d7fcaa492f7">More...</a><br/></td></tr>
<tr class="separator:gaa767ee25aa648007b1341d7fcaa492f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0345340d970a5e3a0aaaba31e63bf3b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga0345340d970a5e3a0aaaba31e63bf3b0">XDSI_ISR_ALLINTR_MASK</a>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="memdesc:ga0345340d970a5e3a0aaaba31e63bf3b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupts mask.  <a href="group__dsi.html#ga0345340d970a5e3a0aaaba31e63bf3b0">More...</a><br/></td></tr>
<tr class="separator:ga0345340d970a5e3a0aaaba31e63bf3b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1ada138c561395450b3c62bf783457d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gae1ada138c561395450b3c62bf783457d">XDSI_ISR_DATA_ID_ERR_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gae1ada138c561395450b3c62bf783457d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Unsupport Data Type.  <a href="group__dsi.html#gae1ada138c561395450b3c62bf783457d">More...</a><br/></td></tr>
<tr class="separator:gae1ada138c561395450b3c62bf783457d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad33056d3b7f5b5d52f465ee6d1a827e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gad33056d3b7f5b5d52f465ee6d1a827e8">XDSI_ISR_PXL_UNDR_RUN_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gad33056d3b7f5b5d52f465ee6d1a827e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Pixel under run.  <a href="group__dsi.html#gad33056d3b7f5b5d52f465ee6d1a827e8">More...</a><br/></td></tr>
<tr class="separator:gad33056d3b7f5b5d52f465ee6d1a827e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDSI_IER_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the interrupt enable masks </p>
</div></td></tr>
<tr class="memitem:ga70eb96c20dcdf636a21fb9140d4798e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga70eb96c20dcdf636a21fb9140d4798e8">XDSI_IER_CMDQ_FIFO_FULL_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga70eb96c20dcdf636a21fb9140d4798e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command queue vacancy full.  <a href="group__dsi.html#ga70eb96c20dcdf636a21fb9140d4798e8">More...</a><br/></td></tr>
<tr class="separator:ga70eb96c20dcdf636a21fb9140d4798e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab30c45469c76c7f5fcd24956466199ed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gab30c45469c76c7f5fcd24956466199ed">XDSI_IER_DATA_ID_ERR_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gab30c45469c76c7f5fcd24956466199ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">Un supported data type.  <a href="group__dsi.html#gab30c45469c76c7f5fcd24956466199ed">More...</a><br/></td></tr>
<tr class="separator:gab30c45469c76c7f5fcd24956466199ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73680e01af90788e31e7d4592f6cd600"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga73680e01af90788e31e7d4592f6cd600">XDSI_IER_PXL_UNDR_RUN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga73680e01af90788e31e7d4592f6cd600"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pixel Under run.  <a href="group__dsi.html#ga73680e01af90788e31e7d4592f6cd600">More...</a><br/></td></tr>
<tr class="separator:ga73680e01af90788e31e7d4592f6cd600"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eed3e0c901d7b2f8b9cb31f3bc73797"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga4eed3e0c901d7b2f8b9cb31f3bc73797">XDSI_IER_ALLINTR_MASK</a>&#160;&#160;&#160;0x00000007</td></tr>
<tr class="memdesc:ga4eed3e0c901d7b2f8b9cb31f3bc73797"><td class="mdescLeft">&#160;</td><td class="mdescRight">All interrupts mask.  <a href="group__dsi.html#ga4eed3e0c901d7b2f8b9cb31f3bc73797">More...</a><br/></td></tr>
<tr class="separator:ga4eed3e0c901d7b2f8b9cb31f3bc73797"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga053204eecdb3569a161927884f46c451"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga053204eecdb3569a161927884f46c451">XDSI_IER_DATA_ID_ERR_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga053204eecdb3569a161927884f46c451"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Unsupport data type.  <a href="group__dsi.html#ga053204eecdb3569a161927884f46c451">More...</a><br/></td></tr>
<tr class="separator:ga053204eecdb3569a161927884f46c451"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad25a30058951dea7bb3138dd2def5f01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gad25a30058951dea7bb3138dd2def5f01">XDSI_IER_PXL_UNDR_RUN_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gad25a30058951dea7bb3138dd2def5f01"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Pixel under run.  <a href="group__dsi.html#gad25a30058951dea7bb3138dd2def5f01">More...</a><br/></td></tr>
<tr class="separator:gad25a30058951dea7bb3138dd2def5f01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDSI_COMMAND_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the short packet command TBD as now </p>
</div></td></tr>
<tr class="memitem:ga698ecf85c35b1bd1e9a98452e7bfa7d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga698ecf85c35b1bd1e9a98452e7bfa7d3">XDSI_SPKTR_DT_MASK</a>&#160;&#160;&#160;0x0000003F</td></tr>
<tr class="memdesc:ga698ecf85c35b1bd1e9a98452e7bfa7d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Type.  <a href="group__dsi.html#ga698ecf85c35b1bd1e9a98452e7bfa7d3">More...</a><br/></td></tr>
<tr class="separator:ga698ecf85c35b1bd1e9a98452e7bfa7d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabd81e18b17e9f396947e2f8b967a4f63"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gabd81e18b17e9f396947e2f8b967a4f63">XDSI_SPKTR_VC_MASK</a>&#160;&#160;&#160;0x000000C0</td></tr>
<tr class="memdesc:gabd81e18b17e9f396947e2f8b967a4f63"><td class="mdescLeft">&#160;</td><td class="mdescRight">Virtual channel number.  <a href="group__dsi.html#gabd81e18b17e9f396947e2f8b967a4f63">More...</a><br/></td></tr>
<tr class="separator:gabd81e18b17e9f396947e2f8b967a4f63"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27fce78971c09f94ed9e7e1a05ba9700"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga27fce78971c09f94ed9e7e1a05ba9700">XDSI_SPKTR_BYTE1_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:ga27fce78971c09f94ed9e7e1a05ba9700"><td class="mdescLeft">&#160;</td><td class="mdescRight">BYTE1 mask.  <a href="group__dsi.html#ga27fce78971c09f94ed9e7e1a05ba9700">More...</a><br/></td></tr>
<tr class="separator:ga27fce78971c09f94ed9e7e1a05ba9700"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga85f26775c68936a9ed66f330b01e31af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga85f26775c68936a9ed66f330b01e31af">XDSI_SPKTR_BYTE2_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:ga85f26775c68936a9ed66f330b01e31af"><td class="mdescLeft">&#160;</td><td class="mdescRight">BYTE2 maks.  <a href="group__dsi.html#ga85f26775c68936a9ed66f330b01e31af">More...</a><br/></td></tr>
<tr class="separator:ga85f26775c68936a9ed66f330b01e31af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60179c017b6e957ca471de7263ea4296"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga60179c017b6e957ca471de7263ea4296">XDSI_SPKTR_DT_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga60179c017b6e957ca471de7263ea4296"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for DataType.  <a href="group__dsi.html#ga60179c017b6e957ca471de7263ea4296">More...</a><br/></td></tr>
<tr class="separator:ga60179c017b6e957ca471de7263ea4296"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaceaab8ceddb1f0642bd2429156d1b7ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gaceaab8ceddb1f0642bd2429156d1b7ff">XDSI_SPKTR_VC_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:gaceaab8ceddb1f0642bd2429156d1b7ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for VC.  <a href="group__dsi.html#gaceaab8ceddb1f0642bd2429156d1b7ff">More...</a><br/></td></tr>
<tr class="separator:gaceaab8ceddb1f0642bd2429156d1b7ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad3423a9a2931ef18ef5698e033aa9da0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gad3423a9a2931ef18ef5698e033aa9da0">XDSI_SPKTR_BYTE1_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gad3423a9a2931ef18ef5698e033aa9da0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for BYTE1.  <a href="group__dsi.html#gad3423a9a2931ef18ef5698e033aa9da0">More...</a><br/></td></tr>
<tr class="separator:gad3423a9a2931ef18ef5698e033aa9da0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga13297e8c2c110f69404cbf9424a468a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga13297e8c2c110f69404cbf9424a468a3">XDSI_SPKTR_BYTE2_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga13297e8c2c110f69404cbf9424a468a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for BYTE2.  <a href="group__dsi.html#ga13297e8c2c110f69404cbf9424a468a3">More...</a><br/></td></tr>
<tr class="separator:ga13297e8c2c110f69404cbf9424a468a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDSI_LTIME_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the Total Line Time </p>
</div></td></tr>
<tr class="memitem:ga4aa0ee6eb41e7de52340066bd78af3b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga4aa0ee6eb41e7de52340066bd78af3b6">XDSI_LTIME_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga4aa0ee6eb41e7de52340066bd78af3b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Total Line time.  <a href="group__dsi.html#ga4aa0ee6eb41e7de52340066bd78af3b6">More...</a><br/></td></tr>
<tr class="separator:ga4aa0ee6eb41e7de52340066bd78af3b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c26d704be758564707d5a0d169c2642"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#ga8c26d704be758564707d5a0d169c2642">XDSI_LTIME_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga8c26d704be758564707d5a0d169c2642"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for DataType.  <a href="group__dsi.html#ga8c26d704be758564707d5a0d169c2642">More...</a><br/></td></tr>
<tr class="separator:ga8c26d704be758564707d5a0d169c2642"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDSI_BBLP_SIZE_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the BLLP Time duration </p>
</div></td></tr>
<tr class="memitem:gabdb4cb3cca3cc63b0768f17d86d2ad78"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gabdb4cb3cca3cc63b0768f17d86d2ad78">XDSI_BLLP_TIME_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gabdb4cb3cca3cc63b0768f17d86d2ad78"><td class="mdescLeft">&#160;</td><td class="mdescRight">BLLP Size.  <a href="group__dsi.html#gabdb4cb3cca3cc63b0768f17d86d2ad78">More...</a><br/></td></tr>
<tr class="separator:gabdb4cb3cca3cc63b0768f17d86d2ad78"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab33892b702ec12e0b363196d16a6467a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dsi.html#gab33892b702ec12e0b363196d16a6467a">XDSI_BLLP_TIME_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gab33892b702ec12e0b363196d16a6467a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for BLLP.  <a href="group__dsi.html#gab33892b702ec12e0b363196d16a6467a">More...</a><br/></td></tr>
<tr class="separator:gab33892b702ec12e0b363196d16a6467a"><td class="memSeparator" colspan="2">&#160;</td></tr>
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